Sasindu Wijeratne


I am a first-year graduate student in the Department of Electrical and Computer Engineering, University of Southern California. I'm working with Professor Viktor Prasanna in FPGA/Parallel Computing Lab. My research interests include developing memory systems for sparse algebraic applications including, tensor decomposition and scalable static/dynamic graph processing. My current research focuses on tensor decomposition on heterogeneous systems.

  • Ph.D. in Electrical and Computer Engineering, 2019 - Present

​               University of Southern California, Los Angeles, USA

  • B.Sc in Electronics and Telecommunication Engineering, 2014 - 2018

               University of Moratuwa, Sri Lanka

Recent News!

  • April 30, 2020 - It was a pleasure to teach CSCI 356: Introduction to Computer Systems with Dr. Marco Paolieri for the 2nd time!

  • April 30, 2020 - Done with my teaching tasks for EE 599: Accelerated Computing Using Field Programmable Gate Arrays with professor Viktor Prasanna, my advisor!

  • May 1, 2021 - Just finished teaching EE 354L: Introduction to Digital Circuits with professor Gandhi Puvvada for the 2nd time!

  • June 24, 2021 - My Paper accepted at HotI28 on programmable memory controller! (acceptance rate: 29%)

  • August 13, 2021 - My paper accepted at HPEC 2021 on Reconfigurable Low-latency Memory System for Sparse Matricized Tensor Times Khatri-Rao Product on FPGA



  • Zhang, R., Wijeratne, S., Yang Y., Kuppannagari S., Prasanna V., 2020, Sept. A High Throughput Parallel Hash Table on FPGA using XOR-based Memory. In Proceedings of the 2020 IEEE High Performance Extreme Computing Conference (HPEC). [Paper]

  • Wijeratne, S., Jayaweera, S., Dananjaya, M., Pasqual, A., 2018, July. Reconfigurable Co-Processor Architecture with Limited Numerical Precision to Accelerate Deep Convolutional Neural Networks. In Proceedings of the 2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP) 2018, Politecnico di Milano, Milan, Italy. [Paper]

  • Senanayake, S., Liyanage, N., Wijeratne, S., Atapattu, S., Athukorala, K., Tharaka, P., Karunaratne, G., Senarath, R., Perera, I., Ekanayake, A., Pasqual, A., 2017, July. High-performance hardware architectures for Intra Block Copy and Palette Coding for HEVC Screen Content Coding Extension. In IEEE 28th International Conference on Application-specific Systems, Architectures and Processors (ASAP) 2017, Seattle, WA, USA. [Paper]

  • Wijeratne, S., Ekanayake, A., Jayaweera, S., Ravishan, D., Pasqual, A., 2019, February. Scalable High-Performance SDN Switch Architecture on FPGA for Core Networks. In FPGA 2019 - 27th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Seaside, California [Abstract]