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Sasindu Wijeratne

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I am a Ph.D. candidate in the Department of Electrical and Computer Engineering, University of Southern California. I'm working with professor Viktor Prasanna in FPGA/Parallel Computing Lab. My research interests include developing parallel algorithms and custom hardware designs for sparse algebraic applications, including tensor decomposition and scalable static/dynamic graph processing. My current research focuses on tensor decomposition on heterogeneous systems.

  • Ph.D. in Electrical and Computer Engineering, 2019 - Present

​               University of Southern California, Los Angeles, USA

  • B.Sc in Electronics and Telecommunication Engineering, 2014 - 2018

               University of Moratuwa, Sri Lanka

Recent News!

  • April 30, 2020 - It was a pleasure to teach CSCI 356: Introduction to Computer Systems with Dr. Marco Paolieri for the 2nd time!

  • April 30, 2020 - Done with my teaching tasks for EE 599: Accelerated Computing Using Field Programmable Gate Arrays with professor Viktor Prasanna

  • June 01, 2021 - Volunteering as a Organizing Committee member for HiPC 2021

  • January 10, 2022 - Volunteering as a Organizing Committee member for HiPC 2022

  • August 13, 2022 - Volunteering as a Organizing Committee member for FCCM 2023

  • Jan 10, 2023 - Started teaching EE 354L: Introduction to Digital Circuits with professor Gandhi Puvvada for the 6th time

  • Jan 31, 2023 - PhD Candidate now

  • Feb 1, 2023: My recent paper will be appear in FPGA 2023!

  • Feb 5, 2023: Received the ACM travel grant to attend FPGA 2023. See you at Monterey!

  • Sept 27, 2023: Selected as an USC MHI Ph.D. Scholar Finalist

  • Sept 30, 2023: My paper, Dynasor, is selected as a best paper candidate at 35th IEEE International Symposium on Computer Architecture and High Performance Computing

  • Nov 30, 2023: Attended DARPA NaPSAC Kick-off Meeting in DC

  • March 01, 2024: Current powerlifting status (Total: 975 LB): 435 LB - Deadlift, 335 LB - Squat, and 205 LB - Bench; (at 165 LB)

Publications:

  • Wijeratne S., Wang T., Kannan R., and Prasanna V.. 2023. Accelerating Sparse MTTKRP for Tensor Decomposition on FPGA. In Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA '23). Association for Computing Machinery, New York, NY, USA. [Paper]

  • Wijeratne, S., Jaiswal, A., Jacob, A., Zhang, B., Prasanna V., 2022, Sept. Performance Modeling Sparse MTTKRP Using Optical Static Random Access Memory on FPGA. In Proceedings of the 2022 IEEE High Performance Extreme Computing Conference (HPEC). [Paper]

  • Wijeratne, S., Wang, T., Kannan, R., Prasanna V., 2022, Sept. Towards Programmable Memory Controller for Tensor Decomposition. In Proceedings of the 12th International Conference on Data Science, Technology and Applications. [Paper]

  • Ye, T., Kuppannagari, S., De Rose, C., Wijeratne, S., Kannan, R., Prasanna V., 2022, Sept. Estimating the Impact of Communication Schemes for Distributed Graph Processing. In Proceedings of IEEE International Symposium on Parallel and Distributed Computing (ISPDC) [Paper]

  • Wijeratne, S., Kannan, R., Prasanna, V., "Reconfigurable Low-latency Memory System for Sparse Matricized Tensor Times Khatri-Rao Product on FPGA," 2021 IEEE High Performance Extreme Computing Conference (HPEC), 2021.

  • Wijeratne, S., Pattnaik, S., Chen, Z., Kannan, R., Prasanna, V., "Programmable FPGA-based Memory Controller," 2021 IEEE Symposium on High-Performance Interconnects (HOTI), 2021.

  • Zhang, R., Wijeratne, S., Yang Y., Kuppannagari S., Prasanna V., 2020, Sept. A High Throughput Parallel Hash Table on FPGA using XOR-based Memory. In Proceedings of the 2020 IEEE High Performance Extreme Computing Conference (HPEC). [Paper]​

  • Wijeratne, S., Jayaweera, S., Dananjaya, M., Pasqual, A., 2018, July. Reconfigurable Co-Processor Architecture with Limited Numerical Precision to Accelerate Deep Convolutional Neural Networks. In Proceedings of the 2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP) 2018, Politecnico di Milano, Milan, Italy. [Paper]​

  • Senanayake, S., Liyanage, N., Wijeratne, S., Atapattu, S., Athukorala, K., Tharaka, P., Karunaratne, G., Senarath, R., Perera, I., Ekanayake, A., Pasqual, A., 2017, July. High-performance hardware architectures for Intra Block Copy and Palette Coding for HEVC Screen Content Coding Extension. In IEEE 28th International Conference on Application-specific Systems, Architectures and Processors (ASAP) 2017, Seattle, WA, USA. [Paper]​

  • Wijeratne, S., Ekanayake, A., Jayaweera, S., Ravishan, D., Pasqual, A., 2019, February. Scalable High-Performance SDN Switch Architecture on FPGA for Core Networks. In FPGA 2019 - 27th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Seaside, California [Abstract]

           

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