Sasindu Wijeratne

Thesis Work:

• Wijeratne, S., Kannan, R., Prasanna, V. (2025). DynaRemap: Hardware Agnostic Parallel Algorithm with Dynamic Tensor Remapping to Accelerate MTTKRP for Sparse Tensor Decomposition. In IEEE Transactions on Parallel and Distributed Systems. [In preparation]

• Wijeratne, S., Kannan, R., Prasanna, V. (2025). Dynasor-GPU: Dynamic Memory Layout for Accelerating sparse MTTKRP for Tensor Decomposition on GPU. In ACM Transactions on Parallel Computing. [In preparation]

• Wijeratne, S., Kannan, R., Prasanna, V. (2025). AMPED: Accelerating MTTKRP for Billion-Scale Sparse Tensor Decomposition on Multiple GPUs. In Proceedings of the 54th International Conference on Parallel Processing. [Accepted]

• Wijeratne, S., Kannan, R., Prasanna, V. (2024). Accelerating Sparse MTTKRP for Small Tensor Decomposition on GPU. In Proceedings of the 2024 Asilomar Conference on Signals, Systems, and Computers. [Best Paper Candidate]

• Wijeratne, S., Kannan, R., Prasanna, V. (2024). Sparse MTTKRP Acceleration for Tensor Decomposition on GPU. In Proceedings of the 21st ACM International Conference on Computing Frontiers.

• Wijeratne, S., Wang, T. Y., Kannan, R., Prasanna, V. (2023). Accelerating Sparse MTTKRP for Tensor Decomposition on FPGA. In Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays.

• Wijeratne, S., Kannan, R., Prasanna, V. (2023). Dynasor: A Dynamic Memory Layout for Accelerating Sparse MTTKRP for Tensor Decomposition on Multi-core CPU. In 35th IEEE International Symposium on Computer Architecture and High Performance Computing. [Best Paper Candidate]

• Wijeratne, S., Wang, T. Y., Kannan, R., Viktor, P. (2022). Towards Programmable Memory Controller for Tensor Decomposition. In 11th International Conference on Data Science, Technology and Applications (DATA’22).

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Other:

• Wijeratne, S., Sundar, S., Kaiser, Md., Jaiswal, A., Mathew, C., Jacob, A. P., Prasanna, V. (2024). Predictive Performance of Photonic SRAM-based In-Memory Computing for Tensor Decomposition. In 2024 IEEE High Performance Extreme Computing Conference (HPEC). [Best Student Paper]

• Wijeratne, S., Jaiswal, A., Jacob, A. P., Zhang, B., Prasanna, V. (2022). Performance modeling sparse MTTKRP using optical static random access memory on FPGA. In 2022 IEEE High Performance Extreme Computing Conference (HPEC).

• Wijeratne, S., Zhang, B., Kannan, R., Prasanna, V., Busart, C. (2023). PAHD: Perception-Action based Human Decision Making using Explainable Graph Neural Networks on SAR images. In Automatic Target Recognition XXXIII.

• Wijeratne, S., Pattnaik, S., Chen, Z., Kannan, R., Prasanna, V. (2021). Programmable fpga-based memory controller. In 2021 IEEE Symposium on High-Performance Interconnects (HOTI).

• Wijeratne, S., Kannan, R., Prasanna, V. (2021). Reconfigurable Low-latency Memory System for Sparse Matricized Tensor Times Khatri-Rao Product on FPGA. In 2021 IEEE High Performance Extreme Computing Conference (HPEC).

• Wijeratne, S., Ekanayake, A., Jayaweera, S., Ravishan, D., Pasqual, A. (2019). Scalable High Perfor- mance SDN Switch Architecture on FPGA for Core Networks. In Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays.

• Wijeratne, S., Jayaweera, S., Dananjaya, M., Pasqual, A. (2018). Reconfigurable co-processor archi- tecture with limited numerical precision to accelerate deep convolutional neural networks. In 2018 IEEE 29Th international conference on application-specific systems, architectures and processors (ASAP).

• Chen, P., Manjunath, P., Wijeratne, S., Zhang, B., Prasanna, V. (2023). Exploiting On-chip Het- erogeneity of Versal Architecture for GNN Inference Acceleration. In 33rd International Conference on Field-Programmable Logic and Applications.

• Zhang, B., Wijeratne, S., Kannan, R., Prasanna, V., Busart, C. (2023). Graph neural network based SAR automatic target recognition with human-in-the-loop. In Algorithms for Synthetic Aperture Radar Imagery XXX.

• Zhang, B., Wijeratne, S., Kannan, R., Prasanna, V., Busart, C. (2023). Graph Neural Network for Accurate and Lowcomplexity SAR ATR. In 15th International Conference on Advanced Geographic Information Systems, Applications, and Services.

• Zhang, B., Wijeratne, S., Kannan, R., Prasanna, V., Busart, C. (2023). How can Human-in-the-loop Improve the Performance of SAR ATR? A Reinforcement Learning Based Approach. In International Radar Conference 2023. [Best Paper Candidate]

• Zhang, B., Jaiswal, A., Mathew, C., Lakkireddy, R., Jacob, A., Wijeratne, S., Prasanna, V. (2022). A high throughput parallel hash table on fpga using xor-based memory. In 2020 IEEE High performance extreme computing conference (HPEC).

• Ye, T., Kuppannagari, S. R., De Rose, C. A., Wijeratne, S., Kannan, R., Prasanna, V. (2022). Estimat- ing the Impact of Communication Schemes for Distributed Graph Processing. In 2022 21st International Symposium on Parallel and Distributed Computing (ISPDC).

• Zhang, R., Wijeratne, S., Yang, Y., Kuppannagari, S. R., Prasanna, V. (2020). A high throughput parallel hash table on fpga using xor-based memory. In 2020 IEEE High performance extreme computing conference (HPEC).

• Senanayake, R., Liyanage, N., Wijeratne, S., Atapattu, S., Ekanayake, A., Pasqual, A. (2017). High performance hardware architectures for Intra Block Copy and Palette Coding for HEVC screen content coding extension. In 2018 IEEE international conference on application-specific systems, architectures and processors (ASAP).